Expose read-latency and write-latency parameters of FIRRTL memories#5133
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trmckay
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Dec 24, 2025
| Seq.fill(numReadPorts)(clock), | ||
| Seq.fill(numWritePorts)(clock), | ||
| Seq.fill(numReadwritePorts)(clock), | ||
| 1, |
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Summary of the changes in this file:
- Add
readLatencyandwriteLatencyto the private impl functions - For each public API
- Set the default latency of 1
- Add a copy of that method with latency parameters passed by the caller
If we expose additional parameters in the future, I think we can keep the minimal public APIs that were present before this PR, then add additional parameters to the new APIs added here.
seldridge
approved these changes
Jan 6, 2026
| * | ||
| * @return A new `SRAMInterface` wire containing the control signals for each instantiated port | ||
| * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle | ||
| * @note Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared. |
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The more Scaladoc way of doing this is:
@throws java.lang.IllegalArgumentException if <the user does something>
mikeurbach
approved these changes
Jan 6, 2026
mikeurbach
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Nice, looks good to me
jackkoenig
approved these changes
Jan 6, 2026
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Contributor Checklist
docs/src?Type of Improvement
Desired Merge Strategy
Release Notes
read-latencyandwrite-latency>= 1Reviewer Checklist (only modified by reviewer)
3.6.x,5.x, or6.xdepending on impact, API modification or big change:7.0)?Enable auto-merge (squash)and clean up the commit message.Create a merge commit.