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[Scala3] Implement ChiselEnum macro#5182

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adkian-sifive/scala3-chiselenum-macro
Jan 29, 2026
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[Scala3] Implement ChiselEnum macro#5182
adkian-sifive merged 4 commits into
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adkian-sifive/scala3-chiselenum-macro

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Move ChiselEnum spec file, failing because Switch macro not merged yet

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Type of Improvement

  • Feature (or new API)
  • Internal or build-related (includes code refactoring/cleanup)

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Release Notes

ChiselEnum now supported in Scala 3

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@adkian-sifive adkian-sifive added the Scala 3 Changes related to upgrading to Scala 3 label Jan 27, 2026
Comment thread core/src/main/scala-3/chisel3/ChiselEnumIntf.scala Outdated
Comment thread plugin/src/main/scala-3/chisel3/internal/plugin/BundlePhase.scala
if !owner.isValDef then report.errorAndAbort("Invalid Value definition")

val name = owner.name.trim
if name.contains(" ") then report.errorAndAbort("Value cannot be called without assigning to an enum")

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Technically this is wrong but I see it's the same behavior in the Scala 2 macro so I'll leave it. But the following should work:

//> using repository https://central.sonatype.com/repository/maven-snapshots
//> using scala 2.13.18
//> using dep org.chipsalliance::chisel:7.7.0+34-94b8570e-SNAPSHOT
//> using plugin org.chipsalliance:::chisel-plugin:7.7.0+34-94b8570e-SNAPSHOT
//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations

import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

object MyEnum extends ChiselEnum {
  val `initial state`, running = Value
}

class Foo extends Module {
  val toggle = IO(Input(Bool()))
  val out = IO(Output(MyEnum()))

  val myReg = RegInit(MyEnum.`initial state`)

  when (toggle) {
    when (myReg === MyEnum.`initial state`) {
      myReg := MyEnum.running
    }.otherwise {
      myReg := MyEnum.`initial state`
    }
  }
  out := myReg
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
    )
  )
}

jackkoenig
jackkoenig previously approved these changes Jan 27, 2026

@jackkoenig jackkoenig left a comment

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I would like more explanation of how the compiler plugin changes fix things, but the macro implementation look good.

@adkian-sifive

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I managed to replicate the compiler crashes independent of ChiselEnum stuff

The original failure has to do with conflicting overriding ValDefs and DefDefs in the same closure. I narrowed the failure to this ChiselEnumSpec test:

class EnumOps(val xType: ChiselEnum, val yType: ChiselEnum) extends Module {
  val io = IO(new Bundle {
   ...
    val eq = Output(Bool())
    val ne = Output(Bool())
  })

which defines vals eq and ne that are Scala 3 compiler keywords defined as DefDefs. Calling asTerm on this ValDef causes an assertion failure in the compiler which checks that asTerm is not called on a method. alternatives lists all overrides so we can disambiguate between the ValDef and the DefDef

@adkian-sifive

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ideally the BundlePhase update should go in separately but it's small enough so imo let's just ship it here

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ideally the BundlePhase update should go in separately but it's small enough so imo let's just ship it here

This actually feels big to me (in that it's subtle and requires special handling), I would appreciate it as its own PR (since I suspect there may be related issues in the future and having a previous example helps).

@jackkoenig jackkoenig dismissed their stale review January 28, 2026 23:56

Want the plugin fix separate, will approve once that's split out.

Move ChiselEnum spec file, failing because Switch macro is not
implemented yet
@adkian-sifive adkian-sifive force-pushed the adkian-sifive/scala3-chiselenum-macro branch from 91ee443 to b148ff7 Compare January 29, 2026 00:56
@adkian-sifive adkian-sifive enabled auto-merge (squash) January 29, 2026 00:58
@adkian-sifive adkian-sifive merged commit 87c663a into main Jan 29, 2026
27 checks passed
@adkian-sifive adkian-sifive deleted the adkian-sifive/scala3-chiselenum-macro branch January 29, 2026 03:55
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2 participants